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| cy8c20x36a/46a/66a/96a capsense ? applications cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-54459 rev. *e revised september 30, 2010 capsense applications features operating range: 1.71 v to 5.5 v low power capsense ? block ? configurable capacitive sensing elements ? supports smartsense ? supports a combination of capsense buttons, sliders, touchpads, touchscreens, and proximity sensors powerful harvard-architecture processor ? m8c cpu speed can be up to 24 mhz or sourced by an external crystal, resonator, or clock signal ? low power at high speed ? interrupt controller ? temperature range: ?40 c to +85 c flexible on-chip memory ? three program/data storage size options: ? cy8c20x36a: 8 kb flash / 1 kb sram ? cy8c20x46a, cy8c20x96a: 16 kb flash/2 kb sram ? cy8c20x66a: 32 kb flash/2 kb sram ? 50,000 flash erase/write cycles ? partial flash updates ? flexible protection modes ? in-system serial programming (issp) full-speed usb ? available on cy8c20646a, cy8c20666a, cy8c20x96a only ? 12 mbps usb 2.0 compliant ? eight unidirectional endpoints ? one bidirectional control endpoint ? dedicated 512 byte buffer ? internally regulated at 3.3 v precision, programmable clocking ? internal main oscillator (imo): 6/12/24 mhz 5% ? internal low speed oscillator (ilo) at 32 khz for watchdog and sleep timers ? precision 32 khz oscillator fo r optional external crystal ? 0.25% accuracy for usb with no external components (cy8c20646a, cy8c20666a, cy8c20x96a only) programmable pin configurations ? up to 36 general-purpose i/os (gpios) (depending on package) ? dual mode gpio: all gpios support digital i/o and analog inputs ? 25-ma sink current on each gpio ? 120 ma total sink current on all gpios ? pull-up, high z, open-drain modes on all gpios ? cmos drive mode ? 5 ma source current on ports 0 and 1 and 1 ma on ports 2, 3, and 4 ? 20 ma total source current on all gpios ? selectable, regulated digital i/o on port 1 ? configurable input threshold on port 1 ? hot-swap capability on all port 1 gpio versatile analog mux ? common internal analog bus ? simultaneous connection of i/o ? high power supply rejection ratio (psrr) comparator ? low-dropout voltage regulator for all analog resources additional system resources ? i 2 c slave: ? selectable to 50 khz, 100 khz, or 400 khz ? no clock stretching (under most conditions) ? implementation during sleep modes with less than 100 a ? hardware address validation ? spi master and slave: configurable 46.9 khz to 12 mhz ? three 16-bit timers ? watchdog and sleep timers ? internal voltage reference ? integrated supervisory circuit ? 8 to 10-bit incremental analog-to-digital converter (adc) ? not available on cy8x20xx6an versions ? two general-purpose high speed, low power analog comparators complete development tools ? free development tool (psoc designer?) ? full-featured, in-cir cuit emulator (ice) and programmer ? full-speed emulation ? complex breakpoint structure ? 128 kb trace memory package options ? cy8c20x36a: ? 16-pin 3 3 0.6 mm qfn ? 24-pin 4 4 0.6 mm qfn ? 32-pin 5 5 0.6 mm qfn ? 48-pin ssop ? 48-pin 7 7 1.0 mm qfn ? cy8c20x46a: ? 16-pin 3 3 0.6 mm qfn ? 24-pin 4 4 0.6 mm qfn ? 30-ball wlcsp ? 32-pin 5 5 0.6 mm qfn ? 48-pin ssop ? 48-pin 7 7 1.0 mm qfn (with usb) ? cy8c20x96a: ? 24-pin 4 4 0.6 mm qfn (with usb) ? 32-pin 5 5 0.6 mm qfn (with usb) ? cy8c20x66a: ? 32-pin 5 5 0.6 mm qfn ? 48-pin 7 7 1.0 mm qfn (with usb) ? 48-pin ssop ? 30-ball wlcsp [+] feedback
cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 2 of 43 logic block diagram capsense system 1k/2k sram interrupt controller sleep and watchdog multiple clock sources internal low speed oscillator (ilo) 6/12/24 mhz internal main oscillator (imo) psoc core cpu core (m8c) supervisory rom (srom) 8k/16k/32k flash nonvolatile memory system resources system bus analog reference system bus port 3 port 2 port 1 port 0 capsense module global analog interconnect 1.8/2.5/3v ldo analog mux two comparators i2c slave spi master/ slave por and lvd usb system resets internal voltage references three 16-bit programmable timers pwrsys (regulator) port 4 digital clocks [1] note 1. internal voltage regulator for internal circuitry [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 3 of 43 contents capsense applications .................................................... 1 features ............................................................................. 1 logic block diagram ........................................................ 2 psoc ? functional overview ............................................ 4 psoc core .................................................................. 4 capsense system ....................................................... 4 additional system resources ..................................... 5 getting started .................................................................. 5 application notes ........................................................ 5 development kits ........................................................ 5 training ....................................................................... 5 cypros consultants .................................................... 5 solutions library .......................................................... 5 technical support ....................................................... 5 designing with psoc designer ....................................... 6 select components ..................................................... 6 configure components .......... .............. .............. ......... 6 organize and connect .............. .............. ........... ......... 6 generate, verify, and debug ....................................... 6 pinouts .............................................................................. 7 16-pin qfn (no e-pad) ............................................ 7 24-pin qfn .............................................................. 8 24-pin qfn with usb ................................................. 9 30-ball part pinout .................................................... 10 32-pin qfn ............................................................. 11 32-pin qfn (with usb) ............................................ 12 48-pin ssop ............................................................ 13 48-pin qfn ............................................................. 14 48-pin qfn with usb .............................................. 15 48-pin qfn ocd ...................................................... 16 electrical specifications ................................................ 17 absolute maximum ratings .... ................................... 17 operating temperature ............................................. 17 dc chip-level specifications .................................... 18 dc gpio specifications ............................................ 19 dc analog mux bus specifications ........................... 21 dc low power comparator sp ecifications ............... 21 comparator user module electrical specifications ... 22 adc electrical specifications ................................... 22 dc por and lvd specifications .............................. 23 dc programming specifications ............................... 23 ac chip-level specifications .................................... 24 ac general purpose i/o specifications .................... 25 ac comparator specifications .................................. 26 ac external clock specifications .............................. 26 ac programming specifications ................................ 27 ac i2c specifications ................................................ 28 packaging information ................................................... 31 thermal impedances ................................................ 34 capacitance on crystal pins .............. .............. ........ 34 solder reflow peak temperat ure ............................. 34 development tool selection .. .............. .............. ........... 35 software .................................................................... 35 development kits ...................................................... 35 evaluation tools ............................................................. 36 device programmers ............. .................................... 36 accessories (emulation and programming) .............. 37 third party tools ....................................................... 37 build a psoc emulator into yo ur board .................... 37 ordering information ...................................................... 38 ordering code definitions .. .......................................... 39 acronymns ...................................................................... 40 acronyms used ......................................................... 40 reference documents .................................................... 40 document conventions ......... .................................... 40 units of measure ....................................................... 40 numeric naming .................... .................................... 41 glossary .......................................................................... 41 document history page ................................................. 42 sales, solutions, and legal information ...................... 43 worldwide sales and design s upport ......... .............. 43 products .................................................................... 43 psoc solutions ......................................................... 43 [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 4 of 43 psoc ? functional overview the psoc family consists of on-chip controller devices, which are designed to replace multiple traditional microcontroller unit (mcu)-based components with one, low cost single-chip programmable component. a psoc device includes configurable analog and digita l blocks, and programmable interconnect. this architecture allows the user to create customized peripheral configurat ions, to match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts. the architecture for this devi ce family, as shown in the logic block diagram on page 2 , consists of three main areas: the core capsense analog system system resources (including a full-speed usb port). a common, versatile bus allows connection between i/o and the analog system. each cy8c20x36a/46a/66a/96a psoc device includes a dedicated capsense block that provides sensing and scanning control circuitry for capacitive sensing applications. depending on the psoc package, up to 36 gpio are also included. the gpio provides access to the mcu and analog mux. psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo and ilo. the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a 4-mips, 8-bit harvard-architecture microprocessor. capsense system the analog system contains the capacitive sensing hardware. several hardware algorithms are supported. this hardware performs capacitive sensing and scanning without requiring external components. the analog system is composed of the capsense psoc block and an internal 1 v or 1.2 v analog reference, which together support capacitive sensing of up to 33 inputs [2] . capacitive sensing is configurable on each gpio pin. scanning of enabled capsense pins are completed quickly and easily across multiple ports. smartsense? smartsense is an innovative solution from cypress that removes manual tuning of capsense applications. this solution is easy to use and provides a robust noise immunity. it is the only auto- tuning solution that establishes, monitors, and maintains all required tuning parameters. smartsense allows engineers to go from prototyping to mass production without re-tuning for manufacturing variations in pcb and/or overlay material properties. figure 1. capsense system block diagram analog multiplexer system the analog mux bus can connect to every gpio pin. pins are connected to the bus individually or in any combination. the bus also connects to the analog system for analysis with the capsense block comparator. switch control logic enables selected pins to precharge continuously under hardware control. this enables capacitive measurement for applications such as touch sensing. other multiplexer applications include: complex capacitive sensing inte rfaces, such as sliders and touchpads. chip-wide mux that allows analog input from any i/o pin. crosspoint connection between any i/o pin combinations. note 2. 36 gpios = 33 pins for capacitive sensing+2 pins for i 2 c + 1 pin for modulator capacitor. idac reference buffer vr cinternal analog global bus cap sense counters comparator mux mux refs capsense clock select oscillator csclk imo cs1 cs2 csn cexternal (p0[1] or p0[3]) [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 5 of 43 additional system resources system resources provide additional capability, such as configurable usb and i 2 c slave, spi master/slave communication interface, three 16-bit programmable timers, and various system resets supported by the m8c. these system resources provide addi tional capability useful to complete systems. additional resources include low voltage detection and power on reset. the merits of each system resource are listed here: the i 2 c slave/spi master-slave module provides 50/100/400 khz communication over two wires. spi communication over three or four wires r uns at speeds of 46.9 khz to 3 mhz (lower for a slower system clock). the i 2 c hardware address recognition feature reduces the already low power consumption by eliminating the need for cpu intervention until a packet addressed to the target device is received. the i 2 c enhanced slave interface appears as a 32-byte ram buffer to the external i 2 c master. using a simple predefined protocol, the master controls t he read and write pointers into the ram. when this method is enabled, the slave does not stall the bus when receiving data bytes in active mode. for usage details, refer to the application note i2c enhanced slave operation - an56007 . low-voltage detection (lvd) interrupts can signal the application of falling voltage levels, while the advanced power- on-reset (por) circuit eliminates the need for a system supervisor. an internal reference provides an absolute reference for capacitive sensing. a register-controlled bypass mode allows the user to disable the ldo regulator. getting started the quickest way to understand psoc silicon is to read this datasheet and then use the psoc designer integrated development environment (ide). this datasheet is an overview of the psoc integrated circuit and presents specific pin, register, and electrical specifications. for in depth information, along with detailed programming details, see the technical reference manual for the cy8c20x36a/46a/66a /96a psoc devices. for up-to-date ordering, packaging, and electrical specification information, see the latest pso c device datasheets on the web at www.cypress.com/psoc . application notes application notes are an excellent introduction to the wide variety of possible psoc designs. they are located at www.cypress.com/psoc . select application notes under the documentation tab. development kits psoc development kits are available online from cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include arrow, avnet, digi- key, farnell, future electronics, and newark. refer to development kits on page 35 . training free psoc and capsense technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training . the training covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to www.cypress.com/cypros . solutions library visit our growing library of solution focused designs at www.cypress.com/solutions . here you can find various application designs that includ e firmware and hardware design files that enable yo u to complete your designs quickly. technical support for assistance with technical issues, search knowledgebase articles and forums at www.cypress.com/support . if you cannot find an answer to your question, create a technical support case or call technical support at 1-800-541-4736. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 6 of 43 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed function mi croprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variet y of user-selectable functions. the psoc development process is summarized in the following four steps: 1. select components 2. configure components 3. organize and connect 4. generate, verify, and debug select components psoc designer provides a library of prebuilt, pretested hardware peripheral components. these components are called user modules. user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and programmable system-on-chip varieties. configure components each of the components you select establishes the basic register settings that implement the select ed function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a timer user module configures one di gital psoc block. the user module parameters permit you to establish the period, mode, and timer clock. configure the parameters and properties to correspond to your chosen application. enter values directly or by selecting values from drop-down menus. user modules are documented in datasheets that are viewed directly in psoc designer. these datasheets explain the internal operation of the compon ent and provide performance specifications. each datasheet de scribes the use of each user module parameter and other information you may need to successfully implement your design. organize and connect you build signal chains by interconnecting user modules to each other and the i/o pins. you perfor m the selection, configuration, and routing so that you have comp lete control over the use of all on-chip resources. generate, verify, and debug when you are ready to test the ha rdware configuration or move to developing code for the project, you perform the ?generate configuration files? step. this causes psoc designer to generate source code that automatic ally configures the device to your specification a nd provides the software for the system. based on your design, software is generated. application programming interfaces (apis) are provided with high level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applications in c, assembly language, or both. the last st ep in the development process takes place inside psoc designer?s debugger (access by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 7 of 43 pinouts the cy8c20x36a/46a/66a/96a psoc device is available in a vari ety of packages, which are listed and illustrated in the following tables. every port pin (labeled with a ?p?) is capable of digital i/o and connection to the common analog bus. however, v ss , v dd , and xres are not capable of digital i/o. 16-pin qfn (no e-pad) table 1. pin definitions ? cy8c20236a, cy8c20246a psoc device pin no. type name description figure 2. cy8c20236a, cy8c20246a psoc device digital analog 1 i/o i p2[5] crystal output (xout) 2 i/o i p2[3] crystal input (xin) 3 iohr i p1[7] i 2 c scl, spi ss 4 iohr i p1[5] i 2 c sda, spi miso 5 iohr i p1[3] spi clk 6 iohr i p1[1] issp clk [3] , i 2 c scl, spi mosi 7 power v ss ground connection 8 iohr i p1[0] issp data [3] , i 2 c sda, spi clk [4] 9 iohr i p1[2] 10 iohr i p1[4] optional external clock (extclk) 11 input xres active high external reset with internal pull-down 12 ioh i p0[4] 13 power v dd supply voltage 14 ioh i p0[7] 15 ioh i p0[3] integrating input 16 ioh i p0[1] integrating input legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. qfn ( top view ) ai , xout, p2[5] ai , i2 c scl, spi ss, p1[7] ai , i2 c sda, spi miso, p1[5] ai, spi cl k ,p1[3] 1 2 3 4 11 10 9 16 15 14 13 p0[3], ai p0[7], ai vdd p0[4] , ai ai, issp clk, spi mosi, p1[1] ai, issp data , i2c sda, spi cl k ,p1[0] p1[2] , ai ai , xin, p2[3] p1[4] , extclk, ai xres p0[1], ai vss 12 5 6 7 8 [3] [3,4] notes 3. on power-up , the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives re sistive low for the next 256 sle ep clock cycles. the scl(p1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts , the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] an d p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 4. alternate spi clock. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 8 of 43 24-pin qfn notes 5. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 6. on power-up , the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives re sistive low for the next 256 sle ep clock cycles. the scl(p1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts , the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] an d p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 7. alternate spi clock. table 2. pin definitions ? cy8c20336a, cy8c20346a [5] pin no. type name description figure 3. cy8c20336a, cy8c20346a psoc device digital analog 1 i/o i p2[5] crystal output (xout) 2 i/o i p2[3] crystal input (xin) 3 i/o i p2[1] 4 iohr i p1[7] i 2 c scl, spi ss 5 iohr i p1[5] i 2 c sda, spi miso 6 iohr i p1[3] spi clk 7 iohr i p1[1] issp clk [6] , i 2 c scl, spi mosi 8 nc no connection 9 power v ss ground connection 10 iohr i p1[0] issp data [6] , i 2 c sda, spi clk [7] 11 iohr i p1[2] 12 iohr i p1[4] optional external clock input (extclk) 13 iohr i p1[6] 14 input xres active high external reset with internal pull-down 15 i/o i p2[0] 16 ioh i p0[0] 17 ioh i p0[2] 18 ioh i p0[4] 19 ioh i p0[6] 20 power v dd supply voltage 21 ioh i p0[7] 22 ioh i p0[5] 23 ioh i p0[3] integrating input 24 ioh i p0[1] integrating input cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. ai, issp data 2 , i2c sda, spi clk, p1[0] qfn (top view) ai, i2c scl, spi ss, p1[7] ai, i2c sda, spi miso, p1[5] ai, spi clk, p1[3] 1 2 3 4 5 6 18 17 16 15 14 13 p0[2], ai p0[0], ai 24 23 22 21 20 19 p0[3], ai p0[5], ai p0[7], ai vdd p0[4], ai 7 8 9 10 11 12 spi mosi, p1[1] ai, p1[2] ai, p2[1] nc p1[6], ai ai, extclk, p1[4] xres p2[0], ai p0[6], ai ai, issp clk 2 , i2c scl p0[1], ai vss ai, xout, p2[5] ai, xin, p2[3] [6, 7] [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 9 of 43 24-pin qfn with usb table 3. pin definition s ? cy8c20396a psoc device [ 8 ] pin no. type name description figure 4. cy8c20396a psoc device digital analog 1 i/o i p2[5] 2 i/o i p2[3] 3 i/o i p2[1] 4 iohr i p1[7] i 2 c scl, spi ss 5 iohr i p1[5] i 2 c sda, spi miso 6 iohr i p1[3] spi clk 7 iohr i p1[1] issp clk [9] , i 2 c scl, spi mosi 8 power v ss ground 9 i/o i d+ usb d+ 10 i/o i d- usb d- 11 power v dd supply 12 iohr i p1[0] issp data [9] , i 2 c sda, spi clk [10] 13 iohr i p1[2] 14 iohr i p1[4] optional external clock input (extclk) 15 iohr i p1[6] 16 reset input xres active high external reset with internal pull-down 17 ioh i p0[0] 18 ioh i p0[2] 19 ioh i p0[4] 20 ioh i p0[6] 21 ioh i p0[7] 22 ioh i p0[5] 23 ioh i p0[3] integrating input 24 ioh i p0[1] integrating input cp power v ss thermal pad must be connected to ground legend i = input, o = output, oh = 5 ma high output drive, r = regulated output p0[7], ai ai, i2 c sda , spi miso , p1[5] d- qfn (top view) ai, i 2 c scl, spi ss, p1[7] ai, spi clk , p1[3] 1 2 3 4 5 6 18 17 16 15 14 13 p0[0], ai xres 24 23 22 21 20 19 p0[3], ai p0[5] p0[6], ai p0[2], ai 7 8 9 10 11 12 ai, issp clk, i2c scl, spi mosi, p1[1] vdd p2 [ 1] , a i vss p1[2 ], ai ai, issp data , i2c sda, spi clk, p1[0] p1[4] , ai, extclk p1[6], ai p0[4], ai p0[1], ai d+ p2 [ 5 ], ai p2 [ 3], ai , ai [9, 10] [9] notes 8. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 9. on power-up , the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives re sistive low for the next 256 sle ep clock cycles. the scl(p1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts , the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] an d p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 10. alternate spi clock. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 10 of 43 30-ball part pinout table 4. pin definitions ? cy8c20766a, cy8c20746a 30-ball part pinout (wlcsp) pin no. type name description digital analog figure 5. cy8c20766a 30-ball wlcsp a1 ioh i p0[2] bottom view top view a2 ioh i p0[6] a3 power v dd supply voltage a4 ioh i p0[1] integrating input a5 i/o i p2[7] b1 i/o i p2[6] b2 ioh i p0[0] b3 ioh i p0[4] b4 ioh i p0[3] integrating input b5 i/o i p2[5] crystal output (xout) c1 i/o i p2[2] c2 i/o i p2[4] c3 ioh i p0[7] c4 ioh i p0[5] c5 i/o i p2[3] crystal input (xin) d1 i/o i p2[0] d2 i/o i p3[0] d3 i/o i p3[1] d4 i/o i p3[3] d5 i/o i p2[1] e1 input xres active high external reset with internal pull-down e2 iohr i p1[6] e3 iohr i p1[4] optional external clock input (ext clk) e4 iohr i p1[7] i 2 c scl, spi ss e5 iohr i p1[5] i 2 c sda, spi miso f1 iohr i p1[2] f2 iohr i p1[0] issp data [11] , i 2 c sda, spi clk [12] f3 power v ss supply ground f4 iohr i p1[1] issp clk [11] , i 2 c scl, spi mosi f5 iohr i p1[3] spi clk 54321 a b c d e f 12345 b c d e f a notes 11. on power-up , the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sl eep clock cycles. the scl(p1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts , the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] an d p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 12. alternate spi clock. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 11 of 43 32-pin qfn table 5. pin definitions ? cy8c20 436a, cy8c20446a, cy8c20466a psoc device [13] pin no. type name description figure 6. cy8c20436a, cy8c20446a, cy8c20466a psoc device digital analog 1 ioh i p0[1] integrating input 2 i/o i p2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o i p3[3] 7 i/o i p3[1] 8 iohr i p1[7] i 2 c scl, spi ss 9 iohr i p1[5] i 2 c sda, spi miso 10 iohr i p1[3] spi clk. 11 iohr i p1[1] issp clk [14] , i 2 c scl, spi mosi. 12 power v ss ground connection. 13 iohr i p1[0] issp data [14] , i 2 c sda, spi clk [15] 14 iohr i p1[2] 15 iohr i p1[4] optional external clock input (extclk) 16 iohr i p1[6] 17 input xres active high external reset with internal pull-down 18 i/o i p3[0] 19 i/o i p3[2] 20 i/o i p2[0] 21 i/o i p2[2] 22 i/o i p2[4] 23 i/o i p2[6] 24 ioh i p0[0] 25 ioh i p0[2] 26 ioh i p0[4] 27 ioh i p0[6] 28 power v dd supply voltage 29 ioh i p0[7] 30 ioh i p0[5] 31 ioh i p0[3] integrating input 32 power v ss ground connection cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. ai, p0[1] ai, p2[7] ai , xout, p2[5] ai, xin, p2[3] ai, p2[1] ai, p3[3] qfn ( top view ) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0 [3 ], ai p0 [7 ], ai vd d p0 [6 ], ai p0 [4 ], ai p0 [2 ], ai ai, p3[1] ai, i2 c scl, spi ss, p1[7] p0[0] , ai p2[6] , ai p3[0] , ai xres ai, i 2c sda , sp i mi so , p 1[ 5] ai, spi clk, p1[3] vss ai , p 1[ 2] ai, e xtclk , p 1[ 4] ai , p 1[ 6] p2[4] , ai p2[2] , ai p2[0] , ai p3[2] , ai p0 [5 ], ai ai , issp clk , i2c scl, spi mosi, p1[1] ai , issp d ata , i2c sda, spi clk, p1[0] [14] [14] notes 13. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 14. on power-up , the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sl eep clock cycles. the scl(p1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts , the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] an d p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 15. alternate spi clock. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 12 of 43 32-pin qfn (with usb) table 6. pin definition s ? cy8c20496a psoc device [16] pin no. type name description figure 7. cy8c20496a psoc device digital analog 1 ioh i p0[1] integrating input 2 i/o i p2[5] xtal out 3 i/o i p2[3] xtal in 4 i/o i p2[1] 5 iohr i p1[7] i 2 c scl, spi ss 6 iohr i p1[5] i 2 c sda, spi miso 7 iohr i p1[3] spi clk 8 iohr i p1[1] issp clk [17] , i 2 c scl, spi mosi 9 power v ss ground pin 10 i i d+ usb d+ 11 d- usb d- 12 power v dd power pin 13 iohr i p1[0] issp data [17] , i 2 c sda, spi clki [18] 14 iohr i p1[2] 15 iohr i p1[4] optional external clock input (extclk) 16 iohr i p1[6] 17 input xres active high external reset with internal pull-down 18 i/o i p3[0] 19 i/o i p3[2] 20 i/o i p2[0] 21 i/o i p2[2] 22 i/o i p2[4] 23 i/o i p2[6] 24 ioh i p0[0] 25 ioh i p0[2] 26 ioh i p0[4] 27 ioh i p0[6] 28 power v dd power pin 29 ioh i p0[7] 30 ioh i p0[5] 31 ioh i p0[3] integrating input 32 power v ss ground pin legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. ai , p 0[ 1 ] xtal out , p 2 [ 5 ] xtal in , p2 [ 3 ] ai , p2 [ 1 ] i2c scl, spi ss , p 1[ 7] i2c sda, spi miso , p 1[ 5 ] qfn (top view ) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0 [3 ], ai p0 [7 ], ai vd d p0 [6 ], ai p0 [4 ], ai p0 [2 ], ai spi clk , p1 [3 ] issp clk, i2c scl, spi mosi,p1 [ 1 ] p0[0] , ai p2[6] , ai p3[0] , ai xres vss usb phy, d+ vd d ai, p 1[ 2] ai, e xtclk, p 1[ 4] ai, p 1[ 6] p2[4] , ai p2[2] , ai p2[0] , ai p3[2] , ai p0 [5 ], ai usb d- issp , d ata, i2c sda, spi clk, p1[0] [17, 18] [17] notes 16. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 17. on power-up , the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sl eep clock cycles. the scl(p1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts , the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] an d p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 18. alternate spi clock. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 13 of 43 48-pin ssop table 7. pin definitions ? cy8c20536 a, cy8c20546a, and cy8c20566a psoc device [19] pin no. digital analog name description figure 8. cy8c20536a, cy8c20546a, and cy8c20566a psoc device 1 ioh i p0[7] 2 ioh i p0[5] 3 ioh i p0[3] integrating input 4 ioh i p0[1] integrating input 5 i/o i p2[7] 6 i/o i p2[5] xtal out 7 i/o i p2[3] xtal in 8 i/o i p2[1] 9 nc no connection 10 nc no connection 11 i/o i p4[3] 12 i/o i p4[1] 13 nc no connection 14 i/o i p3[7] 15 i/o i p3[5] 16 i/o i p3[3] 17 i/o i p3[1] 18 nc no connection 19 nc no connection 20 iohr i p1[7] i 2 c scl, spi ss 21 iohr i p1[5] i 2 c sda, spi miso 22 iohr i p1[3] spi clk 23 iohr i p1[1] issp clk [19] , i 2 c scl, spi mosi 24 v ss ground pin 25 iohr i p1[0] issp data [19] , i 2 c sda, spi clk [20] 26 iohr i p1[2] 27 iohr i p1[4] optional external clock input ( ext clk) 28 iohr i p1[6] 29 nc no connection 30 nc no connection 31 nc no connection 32 nc no connection pin no. digital analog name description 33 nc no connection 41 i/o i p2[2] 34 nc no connection 42 i/o i p2[4] 35 xres active high external reset with internal pull- down 43 i/o i p2[6] 36 i/o i p3[0] 44 ioh i p0[0] 37 i/o i p3[2] 45 ioh i p0[2] 38 i/o i p3[4] 46 ioh i p0[4] 39 i/o i p3[6] 47 ioh i p0[6] 40 i/o i p2[0] 48 power v dd power pin legend a = analog, i = input, o = output, nc = no connection, h = 5 ma high output drive, r = regulated output option. ssop ai, p0[7] vdd ai, p0[5] p0[6] , ai ai, p0[3] p0[4] , ai ai p0[1] p0[2] , ai ai, p2[7] p0[0] , ai xtalout, p2[5] p2[6] , ai xtalin, p2[3] p2[4] , ai ai , p2[1] p2[2] , ai nc p2[0] , ai nc p3[6] , ai ai, p4[3] p3[4] , ai ai, p4[1] p3[2] , ai nc p3[0] , ai ai, p3[7] xres ai, p3[5] nc ai, p3[3] nc ai, p3[1] nc nc nc nc nc i2 c scl, spi ss, p1[7] nc i2 c sda, spi miso, p1[5 ] p1[6] , ai spi clk, p1[3] p1[4] , ext clk issp clk, i2 c scl, spi mosi, p1[1 ] p1[2] , ai vss p1[0] , issp data, i2c sda, spi clk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 43 44 42 40 41 39 38 37 36 35 33 34 32 31 30 29 28 27 26 25 [19, 20] [19] notes 19. on power-up , the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sl eep clock cycles. the scl(p1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts , the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] an d p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 20. alternate spi clock. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 14 of 43 48-pin qfn table 8. pin definition s ? cy8c20636a psoc device [21, 22] pin no. digital analog name description figure 9. cy8c20636a psoc device 1 nc no connection 2 i/o i p2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o i p4[3] 7 i/o i p4[1] 8 i/o i p3[7] 9 i/o i p3[5] 10 i/o i p3[3] 11 i/o i p3[1] 12 iohr i p1[7] i 2 c scl, spi ss 13 iohr i p1[5] i 2 c sda, spi miso 14 nc no connection 15 nc no connection 16 iohr i p1[3] spi clk 17 iohr i p1[1] issp clk [21] , i 2 c scl, spi mosi 18 power v ss ground connection 19 dnu 20 dnu 21 power v dd supply voltage 22 iohr i p1[0] issp data [21] , i 2 c sda, spi clk [23] 23 iohr i p1[2] 24 iohr i p1[4] optional external clock input (extclk) 25 iohr i p1[6] 26 input xres active high external reset with internal pull-down 27 i/o i p3[0] 28 i/o i p3[2] 29 i/o i p3[4] pin no. digital analog name description 30 i/o i p3[6] 40 ioh i p0[6] 31 i/o i p4[0] 41 power v dd supply voltage 32 i/o i p4[2] 42 nc no connection 33 i/o i p2[0] 43 nc no connection 34 i/o i p2[2] 44 ioh i p0[7] 35 i/o i p2[4] 45 ioh i p0[5] 36 i/o i p2[6] 46 ioh i p0[3] integrating input 37 ioh i p0[0] 47 power v ss ground connection 38 ioh i p0[2] 48 ioh i p0[1] 39 ioh i p0[4] cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive, r = regulated output. qfn ( top view ) vss p0[3], ai p0[5], ai p0[7], ai vdd p0[6], ai p0[2], ai p0[0], ai 10 11 12 ai , p2[7] nc ai , xout, p2[5] ai , xin , p2[3] ai , p2[1] ai , p4[3] ai , p4[1] ai , p3[7] ai , p3[5] ai , p3[3] ai p 3[1] ai , i2 c scl, spi ss, p1[ 7] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 4 6 45 44 43 42 41 4 0 39 38 37 p2[4] , ai p2[2] , ai p2[0] , ai p4[2] , ai p4[0] , ai p3[6] , ai p3[4] , ai p3[2] , ai p3[0 ], ai xres p1[6] , ai p2[6] , ai 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 i2c sda, spi miso, a i, p1[5] nc spiclk,ai,p1[3] ai , issp cl k ,i2cscl,spimosi,p1[1] vss dnu dnu vdd ai, issp data 1 ,i2csda,spicl k ,p1[0] ai, p1[2] ai, extclk, p1[4] nc nc nc p0[4], ai p0[1], ai [21] [21, 23] notes 21. on power-up , the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sl eep clock cycles. the scl(p1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts , the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] an d p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 22. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal 23. alternate spi clock. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 15 of 43 48-pin qfn with usb table 9. pin definitions ? cy8c20646a, cy8c20666a psoc device [24, 25] pin no. digital analog name description figure 10. cy8c20646a, cy8c20666a psoc device 1 nc no connection 2 i/o i p2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o i p4[3] 7 i/o i p4[1] 8 i/o i p3[7] 9 i/o i p3[5] 10 i/o i p3[3] 11 i/o i p3[1] 12 iohr i p1[7] i 2 c scl, spi ss 13 iohr i p1[5] i 2 c sda, spi miso 14 nc no connection 15 nc no connection 16 iohr i p1[3] spi clk 17 iohr i p1[1] issp clk [ 24 ] , i 2 c scl, spi mosi 18 power v ss ground connection 19 i/o d+ usb d+ 20 i/o d- usb d- 21 power v dd supply voltage 22 iohr i p1[0] issp data [ 24 ] , i 2 c sda, spi clk [ 26 ] 23 iohr i p1[2] 24 iohr i p1[4] optional external clock input (extclk) 25 iohr i p1[6] 26 input xres active high external reset with internal pull-down 27 i/o i p3[0] 28 i/o i p3[2] 29 i/o i p3[4] pin no. digital analog name description 30 i/o i p3[6] 40 ioh i p0[6] 31 i/o i p4[0] 41 power v dd supply voltage 32 i/o i p4[2] 42 nc no connection 33 i/o i p2[0] 43 nc no connection 34 i/o i p2[2] 44 ioh i p0[7] 35 i/o i p2[4] 45 ioh i p0[5] 36 i/o i p2[6] 46 ioh i p0[3] integrating input 37 ioh i p0[0] 47 power v ss ground connection 38 ioh i p0[2] 48 ioh i p0[1] 39 ioh i p0[4] cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive, r = regulated output. qfn vss p0[3], ai p0[5 ], ai p0[7], ai vdd p0[6], ai p0[2], ai p0[0], ai ai , p2[7] nc ai, xout, p2[5] ai, xin , p2[3] ai , p2[1] ai , p4[3] ai , p4[1] ai , p3[7] ai , p3[5] ai , p3[3] ai , p3[1] ai, i2 c scl, spi ss, p1[7] 35 34 33 32 36 48 47 46 45 44 43 42 41 40 39 38 37 p2[4] , ai p2[2] , ai p2[0] , ai p4[2] , ai p2[6] , ai 1 2 3 4 5 nc nc p0[4], ai p0[1], ai ( top view ) 10 11 12 31 30 29 28 27 26 25 p4[0] , ai p3[6] , ai p3[4] , ai p3[2] , ai p3[0 ], ai xres p1[6] , ai 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 i2csda,spimiso,ai,p1[5] nc spi clk, a i, p1[3] ai , issp cl k , i2c scl, spi mosi, p1[1] vss d+ d- vdd ai , issp d ata, i2c sda, spi cl k ,p1[0] ai, p 1[2] ai, extclk, p1[4] nc [24, 26] [24] notes 24. on power-up , the sda(p1[0]) drives a strong high for 256 sl eep clock cycles and drives resistive low for the next 256 sl eep clock cycles. the scl(p1[1])line drives resistive low for 512 sleep clock cycles and both the pins transiti on to high impedance state . on reset, after xres de- asser ts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high imped ance state. in both cases, a pull-up resistance on these li nes combines with the pull-down resistance (5.6k ohm) and form a potential divider. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use al ternate pins if you encounter issues. 25. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 26. alternate spi clock. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 16 of 43 48-pin qfn ocd the 48-pin qfn part is for the cy8c20066a on-chip debug (ocd) psoc device. note that this part is only used for in-circuit debugging. table 10. pin definitions ? cy8c20066a psoc device [27, 28] pin no. digital analog name description figure 11. cy8c20066a psoc device 1 ocdoe ocd mode direction pin 2 i/o i p2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o i p4[3] 7 i/o ip4[1] 8 i/o i p3[7] 9 i/o i p3[5] 10 i/o i p3[3] 11 i/o i p3[1] 12 iohr i p1[7] i 2 c scl, spi ss 13 iohr i p1[5] i 2 c sda, spi miso 14 cclk ocd cpu clock output 15 hclk ocd high speed clock output 16 iohr i p1[3] spi clk. 17 iohr i p1[1] issp clk [ 29 ], i 2 c scl, spi mosi 18 power v ss ground connection 19 i/o d+ usb d+ 20 i/o d- usb d- 21 power v dd supply voltage 22 iohr i p1[0] issp data [ 29 ] , i 2 c sda, spi clk [ 30 ] 23 iohr i p1[2] pin no. digital analog name description 24 iohr i p1[4] optional external clock input (extclk) 37 ioh i p0[0] 25 iohr i p1[6] 38 ioh i p0[2] 26 input xres active high external reset with internal pull-down 39 ioh i p0[4] 27 i/o i p3[0] 40 ioh i p0[6] 28 i/o ip3[2] 41 power v dd supply voltage 29 i/o ip3[4] 42 ocdo ocd even data i/o 30 i/o ip3[6] 43 ocde ocd odd data output 31 i/o i p4[0] 44 ioh i p0[7] 32 i/o i p4[2] 45 ioh i p0[5] 33 i/o i p2[0] 46 ioh i p0[3] integrating input 34 i/o i p2[2] 47 power v ss ground connection 35 i/o i p2[4] 48 ioh i p0[1] 36 i/o i p2[6] cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive, r = regulated output. notes 27. this part is available in limited quantities for in-circuit debugging during prototype development. it is not available in p roduction volumes. 28. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 29. on power-up , the sda(p1[0]) drives a strong high for 256 sl eep clock cycles and drives resistive low for the next 256 sl eep clock cycles. the scl(p1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state . on reset, after xres de- asser ts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high impedanc e state. in both cases, a pull-up resistance on these li nes combines with the pull-down resistance (5.6k ohm) and form a potential divider. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use al ternate pins if you encounter issues. 30. alternate spi clock. qfn ( top view ) vss p0[3], ai p0[5 ], ai p0[7], ai vdd p0[6], ai p0[2], ai p0[0], ai 10 11 12 a i , p2[7] ai, xout, p2[5] ai, xin , p2[3] ai , p2[1] ai , p4[3] ai , p4[1] ai , p3[7] ai, p3[5] ai, p3[3] ai, p3[1] ai, i2 c scl, spi ss, p1[7] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p2[4] , ai p2[2] , ai p2[0] , ai p4[2] , ai p4[0] , ai p3[6] , ai p3[4] , ai p3[2] , ai p3[0] , ai xres p1[6] , ai p2[6] , ai 1 2 3 4 5 6 7 8 9 1 3 14 15 16 17 18 19 20 21 22 23 24 i2csda,spimiso,ai,p1[5] spi clk, a i, p1[3] ai , issp clk 6 ,i2cscl,spimosi,p1[1] vss d+ d- vdd ai,issp data 1 , i2c sda, spi clk, p1[0] ai, p 1[2] ai, extclk, p1[4] p0[4], ai p0[1], ai ocdo e cclk hclk ocde ocdo [29, 30] [29] [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 17 of 43 electrical specifications this section presents the dc and ac electric al specifications of the cy 8c20x36a/46a/66a/96a psoc devices. for the latest electr ical specifications, confirm that you have the mo st recent datasheet by visiting the web at http://www.cypress.com/psoc . figure 12. voltage versus cpu frequency absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. operating temperature 5.5v 750 khz 24 mhz cpu frequency vdd voltage 1.71v 3 mhz v a l i d o p e r a t i n g r e g i o n table 11. absolute maximum ratings symbol description conditions min typ max units t stg storage temperature higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temper atures above 85 c degrades reliability. ?55 +25 +125 c v dd supply voltage relative to v ss ? ?0.5 ? +6.0 v v io dc input voltage ? v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tristate ? v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any port pin ? ?25 ? +50 ma esd electro static discharge voltage human body model esd 2000 ? ? v lu latch-up current in accordance with jesd78 standard ? ? 200 ma table 12. operating temperature symbol description conditions min typ max units t a ambient temperature ? ?40 ? +85 c t c commercial temperature range ? 0 70 c t j operational die temperature the temperature rise from ambient to junction is package specific. refer the table thermal impedances per package on page 34 . the user must limit the power consumption to comply with this requirement. ?40 ? +100 c [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 18 of 43 dc chip-level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 13. dc chip-level specifications symbol description conditions min typ max units v dd [31, 32, 33, 34] supply voltage refer the table dc por and lvd specifications on page 23 1.71 ? 5.50 v i dd24 supply current, imo = 24 mhz conditions are v dd 3.0 v, t a = 25 c, cpu = 24 mhz. capsense running at 12 mhz, no i/o sourcing current ? 3.32 4.00 ma i dd12 supply current, imo = 12 mhz conditions are v dd 3.0 v, t a = 25 c, cpu = 12 mhz. capsense running at 12 mhz, no i/o sourcing current ? 1.86 2.60 ma i dd6 supply current, imo = 6 mhz conditions are v dd 3.0 v, t a = 25 c, cpu = 6 mhz. capsense running at 6 mhz, no i/o sourcing current ? 1.13 1.80 ma i sb0 deep sleep current v dd 3.0 v, t a = 25 c, i/o regulator turned off ? 0.10 0.50 a i sb1 standby current with por, lvd and sleep timer v dd 3.0 v, t a = 25 c, i/o regulator turned off ? 1.07 1.50 a notes 31. when v dd remains in the range from 1.71 v to 1.9 v fo r more than 50 sec, the slew rate when moving from the 1.71 v to 1.9 v range to g reater than 2 v must be slower than 1 v/500 usec to avoid triggering por. the only ot her restriction on slew rates for any other voltage range or trans ition is the sr power_up parameter. 32. if powering down in standby sleep mode, to properly detect and recover from a v dd brown out condition any of the following actions must be taken: a. bring the device out of sleep before powering down. b. assure that v dd falls below 100 mv before powering back up. c. set the no buzz bit in the osc_cr0 register to keep the voltage monitoring circuit powered during sleep. d. increase the buzz rate to assure that the falling edge of v dd is captured. the rate is configured thr ough the pssdc bits in the slp_cfg register. for the referenced registers, refer to the cy8c20x36 technical reference manual . in deep sleep mode, additional low power voltage monitoring circuitry allows v dd brown out conditions to be detected for edge rates slower than 1v/ms. 33. afor usb mode, the v dd supply for bus-powered application should be limit ed to 4.35v-5.35v. for self-powered application, v dd should be 3.15 v-3.45 v. 34. for proper capsense block functionality, if the drop in v dd exceeds 5% of the base v dd , the rate at which v dd drops should not exceed 200 mv/s. base v dd can be between 1.8 v and 5.5 v [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 19 of 43 dc gpio specifications the following tables list guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 3.0 v to 5.5 v and ?40 c t a 85 c, 2.4 v to 3.0 v and ?40 c t a 85 c, or 1.71 v to 2.4 v and ?40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3 v at 25 c and are for design guidance only. table 14. 3.0-v to 5.5-v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k v oh1 high output voltage port 2 or 3 pins ioh < 10 a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh2 high output voltage port 2 or 3 pins ioh = 1 ma, maximum of 20 ma source current in all i/os v dd ? 0.90 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh < 10 a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 5 ma, maximum of 20 ma source current in all i/os v dd ? 0.90 ? ? v v oh5 high output voltage port 1 pins with ldo regulator enabled for 3 v out ioh < 10 a, v dd > 3.1 v, maximum of 4 i/os all sourcing 5 ma 2.85 3.00 3.30 v v oh6 high output voltage port 1 pins with ldo regulator enabled for 3 v out ioh = 5 ma, v dd > 3.1v, maximum of 20 ma source current in all i/os 2.20 ? ? v v oh7 high output voltage port 1 pins with ldo enabled for 2.5 v out ioh < 10 a, v dd > 2.7 v, maximum of 20 ma source current in all i/os 2.35 2.50 2.75 v v oh8 high output voltage port 1 pins with ldo enabled for 2.5 v out ioh = 2 ma, v dd > 2.7 v, maximum of 20 ma source current in all i/os 1.90 ? ? v v oh9 high output voltage port 1 pins with ldo enabled for 1.8 v out ioh < 10 a, v dd > 2.7 v, maximum of 20 ma source current in all i/os 1.60 1.80 2.10 v v oh10 high output voltage port 1 pins with ldo enabled for 1.8 v out ioh = 1 ma, v dd > 2.7 v, maximum of 20 ma source current in all i/os 1.20 ? ? v v ol low output voltage iol = 25 ma, v dd > 3.3 v, maximum of 60 ma sink current on even port pins (for example, p0[2] and p1[4]) and 60 ma sink current on odd port pins (for example, p0[3] and p1[5]) ??0.75v v il input low voltage ? ? ? 0.80 v v ih input high voltage ? 2.00 ? ? v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 0.001 1 a c pin pin capacitance package and pin dependent te m p = 2 5 c 0.50 1.70 7 pf [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 20 of 43 table 15. 2.4v to 3.0v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k v oh1 high output voltage port 2 or 3 pins ioh < 10 a, maximum of 10 ma source current in all i/os v dd - 0.20 ? ? v v oh2 high output voltage port 2 or 3 pins ioh = 0.2 ma, maxi mum of 10 ma source current in all i/os v dd - 0.40 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh < 10 a, maximum of 10 ma source current in all i/os v dd - 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 2 ma, maximum of 10 ma source current in all i/os v dd - 0.50 ? ? v v oh5a high output voltage port 1 pins with ldo enabled for 1.8 v out ioh < 10 a, v dd > 2.4 v, maximum of 20 ma source current in all i/os 1.50 1.80 2.10 v v oh6a high output voltage port 1 pins with ldo enabled for 1.8 v out ioh = 1 ma, v dd > 2.4 v, maximum of 20 ma source current in all i/os 1.20 ? ? v v ol low output voltage iol = 10 ma, maximum of 30 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.75 v v il input low voltage ? ? ? 0.72 v v ih input high voltage ? 1.40 ? v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 1 1000 na c pin capacitive load on pins package and pin dependent te m p = 2 5 c 0.50 1.70 7 pf table 16. 1.71-v to 2.4-v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k v oh1 high output voltage port 2 or 3 pins ioh = 10 a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh2 high output voltage port 2 or 3 pins ioh = 0.5 ma, maximum of 10 ma source current in all i/os v dd ? 0.50 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 100 a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 2 ma, maximum of 10 ma source current in all i/os v dd ? 0.50 ? ? v v ol low output voltage iol = 5 ma, maximum of 20 ma sink current on even port pi ns (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.40 v v il input low voltage ? ? ? 0.30 v dd v v ih input high voltage ? 0.65 v dd ??v [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 21 of 43 dc analog mux bus specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. dc low power comparat or specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 1 1000 na c pin capacitive load on pins package and pin dependent temp = 25 o c 0.50 1.70 7 pf table 16. 1.71-v to 2.4-v dc gpio specifications (continued) symbol description conditions min typ max units table 17. dc characteristics ? usb interface symbol description conditions min typ max units r usbi usb d+ pull-up resistance with idle bus 900 ? 1575 r usba usb d+ pull-up resistance while receiving traffic 1425 ? 3090 v ohusb static output high ? 2.8 ?3.6v v olusb static output low ? ? ?0.3v v di differential input sensitivity ? 0.2 ?v v cm differential input common mode range ? 0.8 ?2.5v v se single ended receiver threshold ? 0.8 ?2.0v c in transceiver capacitance ? ? ?50pf i io high z state data line leakage on d+ or d- line ?10 ?+10 a r ps2 ps/2 pull-up resistance ? 3000 5000 7000 r ext external usb series resistor in series with each usb pin 21.78 22.0 22.22 table 18. dc analog mux bus specifications symbol description conditions min typ max units r sw switch resistance to common analog bus ? ? ? 800 r gnd resistance of initialization switch to v ss ? ? ? 800 the maximum pin voltage for measuring r sw and r gnd is 1.8 v table 19. dc comparator specifications symbol description conditions min typ max units v lpc low power comparator (lpc) common mode maximum voltage limited to v dd 0.0 ? 1.8 v i lpc lpc supply current ? ? 10 40 a v oslpc lpc voltage offset ? ? 2.5 30 mv [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 22 of 43 comparator user module electrical sp ecifications the following table lists the guaranteed maximum and minimum spec ifications. unless stated otherwis e, the specifications are fo r the entire device voltage and temperature operatin g range: ?40c <= ta <= 85c, 1.71v <= v dd <= 5.5v. adc electrical sp ecifications table 20. comparator user module electrical specifications symbol description conditions min typ max units t comp comparator response time 50 mv overdrive ? 70 100 ns offset valid from 0.2 v to v dd ? 0.2 v ? 2.5 30 mv current average dc current, 50 mv overdrive ? 20 80 a psrr supply voltage > 2 v power supply rejection ratio ? 80 ? db supply voltage < 2 v power supply rejection ratio ? 40 ? db input range ? 0 1.5 v table 21.adc user module electrical specifications symbol description conditions min typ max units input v in input voltage range ? 0 ? vrefadc v c iin input capacitance ???5 pf r in input resistance equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution 1/(500ff data clock) 1/(400ff data clock) 1/(300ff data clock) reference v refadc adc reference voltage ? 1.14 ? 1.26 v conversion rate f clk data clock source is chip?s internal main oscillator. see ac chip-level specifications for accuracy 2.25 ? 6 mhz s8 8-bit sample rate data clock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) ?23.43 ?ksps s10 10-bit sample rate da ta clock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) ? 5.85 ? ksps dc accuracy res resolution can be set to 8-, 9-, or 10-bit 8 ? 10 bits dnl differential nonlinearity ? ?1 ? +2 lsb inl integral nonlinearity ? ?2 ? +2 lsb e offset offset error 8-bit resolution 0 3.20 19.20 lsb 10-bit resolution 0 12.80 76.80 lsb e gain gain error for any resolution ?5 ? +5 %fsr power i adc operating current ? ? 2.10 2.60 ma psrr power supply rejection ratio psrr (v dd > 3.0 v) ? 24 ? db psrr (v dd < 3.0 v) ? 30 ? db [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 23 of 43 dc por and lvd specifications the following table lists guaranteed maximum and minimum specif ications for the entire voltage and temperature ranges. dc programming specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 22. dc por and lvd specifications symbol description conditions min typ max units v por0 1.66 v selected in psoc designer v dd must be greater than or equal to 1.71 v during startup, reset from the xres pin, or reset from watchdog. 1.61 1.66 1.71 v v por1 2.36 v selected in psoc designer ? 2.36 2.41 v por2 2.60 v selected in psoc designer ? 2.60 2.66 v por3 2.82 v selected in psoc designer ? 2.82 2.95 v lvd0 2.45 v selected in psoc designer ? 2.40 2.45 2.51 v v lvd1 2.71 v selected in psoc designer 2.64 [35] 2.71 2.78 v lvd2 2.92 v selected in psoc designer 2.85 [36] 2.92 2.99 v lvd3 3.02 v selected in psoc designer 2.95 [37] 3.02 3.09 v lvd4 3.13 v selected in psoc designer 3.06 3.13 3.20 v lvd5 1.90 v selected in psoc designer 1.84 1.90 2.32 v lvd6 1.80 v selected in psoc designer 1.75 [38] 1.80 1.84 v lvd7 4.73 v selected in psoc designer 4.62 4.73 4.83 table 23. dc programming specifications symbol description conditions min typ max units v ddiwrite supply voltage for flash write operations ? 1.71 ? 5.25 v i ddp supply current during programming or verify ? ? 5 25 ma v ilp input low voltage during programming or verify see the appropriate dc gpio specifica- tions on page 19 ? ? v il v v ihp input high voltage during programming or verify see appropriate dc gpio specifications on page 19 table on pages 15 or 16 v ih ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify driving internal pull-down resistor ? ? 0.2 ma i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify driving internal pull-down resistor ? ? 1.5 ma v olp output low voltage during programming or verify ? ? v ss + 0.75 v v ohp output high voltage during programming or verify see appropriate dc gpio specifications on page 19 table on page 16. for v dd > 3v use v oh4 in table 12 on page 17. v oh ? v dd v flash enpb flash write endurance erase/write cycles per block 50,000 ? ? ? flash dr flash data retention following maximum flash write cycles; ambient temperature of 55 c 20 ? ? years notes 35. always greater than 50 mv above v ppor1 voltage for falling supply. 36. always greater than 50 mv above v ppor2 voltage for falling supply. 37. always greater than 50 mv above v ppor3 voltage for falling supply. 38. always greater than 50 mv above v ppor0 voltage for falling supply. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 24 of 43 ac chip-level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 24. ac chip-level specifications symbol description conditions min typ max units f imo24 internal main oscillator frequency at 24 mhz setting ? 22.8 24 25.2 mhz f imo12 internal main oscillator frequency at 12 mhz setting ? 11.4 12 12.6 mhz f imo6 internal main oscillator frequency at 6 mhz setting ? 5.7 6.0 6.3 mhz f cpu cpu frequency ? 0.75 ? 25.20 mhz f 32k1 internal low speed oscillator frequency ? 19 32 50 khz f 32k_u internal low speed oscillator (ilo) untrimmed frequency) ? 13 32 82 khz dc imo duty cycle of imo ? 40 50 60 % dc ilo internal low speed oscillator duty cycle ? 40 50 60 % sr power_up power supply slew rate v dd slew rate during power-up ? ? 250 v/ms t xrst external reset pulse width at power-up after supply voltage is valid 1 ? ? ms t xrst2 external reset pulse width after power-up [39] applies after part has booted 10 ? ? s note 39. the minimum required xres pulse length is longer when programming the device (see table 30 on page 27 ). [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 25 of 43 ac general purpose i/o specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. figure 13. gpio timing diagram table 25. ac gpio specifications symbol description conditions min typ max units f gpio gpio operating frequency normal strong mode port 0, 1 0 0 ? ? 6 mhz for 1.71 v cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 27 of 43 ac programming specifications figure 14. ac waveform the following table lists the guaranteed maximum and minimum spec ifications for the entire volt age and temperature ranges. table 30. ac programming specifications symbol description conditions min typ max units t rsclk rise time of sclk ? 1 ? 20 ns t fsclk fall time of sclk ? 1 ? 20 ns t ssclk data setup time to falling edge of sclk ? 40 ? ? ns t hsclk data hold time from falling edge of sclk ? 40 ? ? ns f sclk frequency of sclk ? 0 ? 8 mhz t eraseb flash erase time (block) ? ? ? 18 ms t write flash block write time ? ? ? 25 ms t dsclk data out delay from falling edge of sclk 3.6 < v dd ? ? 60 ns t dsclk3 data out delay from falling edge of sclk 3.0 v dd 3.6 ? ? 85 ns t dsclk2 data out delay from falling edge of sclk 1.71 v dd 3.0 ? ? 130 ns t xrst3 external reset pulse width after power-up required to enter programming mode when coming out of sleep 300 ? ? s t xres xres pulse length ? 300 ? ? s t vddwait v dd stable to wait-and-poll hold off ? 0.1 ? 1 ms t vddxres v dd stable to xres assertion delay ? 14.27 ? ? ms t poll sdata high pulse time ? 0.01 ? 200 ms t acq ?key window? time after a v dd ramp acquire event, based on 256 ilo clocks. ? 3.20 ? 19.60 ms t xresini ?key window? time after an xres event, based on 8 ilo clocks ? 98 ? 615 s sclk (p1[1]) t rsclk t fsclk sdata (p1[0]) t ssclk t hsclk t dsclk [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 28 of 43 ac i 2 c specifications the following table lists guaranteed maximum and minimum specificat ions for the entire voltage and temperature ranges. figure 15. definition for timing for fast/standard mode on the i 2 c bus table 31. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units min max min max f scl scl clock frequency 0 100 0 400 khz t hd;sta hold time (repeated) start condition. afte r this period, the first clock pulse is generated 4.0 ?0.6 ?s t low low period of the scl clock 4.7 ?1.3 ?s t high high period of the scl clock 4.0 ?0.6 ?s t su;sta setup time for a repeated start condition 4.7 ?0.6 ?s t hd;dat data hold time 0 3.45 0 0.90 s t su;dat data setup time 250 ? 100 [41] ?ns t su;sto setup time for stop condition 4.0 ?0.6 ?s t buf bus free time between a stop and start condition 4.7 ?1.3 ?s t sp pulse width of spikes are suppressed by the input filter ? ?050ns note 41. a fast-mode i 2 c-bus device can be used in a standard mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this automatically be the case if the device does not stre tch the low period of the scl signal. if such devi ce does stretch the low period of the scl sig nal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) befor e the scl line is released. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 29 of 43 figure 16. spi master mode 0 and 2 figure 17. spi master mode 1 and 3 table 32. spi master ac specifications symbol description conditions min typ max units f sclk sclk clock frequency v dd 2.4 v v dd < 2.4 v ? ? ? ? 6 3 mhz mhz dc sclk duty cycle ? ? 50 ? % t setup miso to sclk setup time v dd 2.4 v v dd < 2.4 v 60 100 ? ? ? ? ns ns t hold sclk to miso hold time ? 40 ? ? ns t out_val sclk to mosi valid time ? ? ? 40 ns t out_high mosi high time ? 40 ? ? ns 1/f sclk t low t high t out_h t hold t setup t out_su msb lsb spi master, modes 0 and 2 sclk (mode 0) sclk (mode 2) miso (input) mosi (output) 1/f sclk t high t low t out_h t hold t setup sclk (mode 1) sclk (mode 3) miso (input) mosi (output) spi master, modes 1 and 3 t out_su msb msb lsb lsb [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 30 of 43 figure 18. spi slave mode 0 and 2 figure 19. spi slave mode 1 and 3 table 33. spi slave ac specifications symbol description conditions min typ max units f sclk sclk clock frequency v dd 2.4 v v dd < 2.4 v ? ? ? ? 12 6 mhz mhz t low sclk low time ? 41.67 ? ? ns t high sclk high time ? 41.67 ? ? ns t setup mosi to sclk setup time ? 30 ? ? ns t hold sclk to mosi hold time ? 50 ? ? ns t ss_miso ss high to miso valid ? ? ? 153 ns t sclk_miso sclk to miso valid ? ? ? 125 ns t ss_high ss high time ? ? ? 50 ns t ss_clk time from ss low to first sclk ? 2/sclk ? ? ns t clk_ss time from last sclk to ss high ? 2/sclk ? ? ns t clk_ss t ss_high 1/f sclk t low t high t out_h t hold t setup t ss_miso t ss_clk msb lsb spi slave, modes 0 and 2 /ss sclk (mode 0) sclk (mode 2) miso (output) mosi (input) t clk_ss 1/f sclk t high t low t sclk_miso t out_h t hold t setup t ss_clk /ss sclk (mode 1) sclk (mode 3) miso (output) mosi (input) spi slave, modes 1 and 3 t ss_miso msb msb lsb lsb [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 31 of 43 packaging information this section illustrates the packaging spec ifications for the cy8c20x36a /46a/66a/96a psoc device, al ong with the thermal imped- ances for each package. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a det ailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress. com/design/mr10161 . figure 20. 16-pin qfn no e-pad 3x3x0.6 mm package outline (sawn) figure 21. 24-pin (4 4 0.6 mm) qfn 1.5 1.5 (nom) pin #1 id 1 2 0.20 min 0.45 0.55 0.30 0.18 0.50 3. dimensions in mm, min max bottom view 1. jedec # mo-220 2. package weight: 0.014g part no. lg16a ld16a description lead-free standard 0.20 dia typ. top view 0.60 max 0.05 max 0.152 ref. seating plane side view 2.9 3.1 2.9 3.1 notes: 1 2 001-09116 *e 001-13937 *c [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 32 of 43 figure 22. 32-pin (5 5 0.6 mm) qfn figure 23. 48-pin (300-mil) ssop 001-42168 *d 0.095 0.025 0.008 seating plane 0.420 0.088 .020 0.292 0.299 0.395 0.092 bsc 0.110 0.016 0.620 0.008 0.0135 0.630 dimensions in inches min. max. 0.040 0.024 0-8 gauge plane .010 1 24 25 48 0.004 0.005 0.010 51-85061 *d [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 33 of 43 figure 24. 48-pin (7 7 1.0 mm) qfn figure 25. 30-ball (2.2 2.32 0.40 mm) wlcsp important notes for information on the preferred dimensions for mountin g qfn packages, see the following application note at http://www.amkor.com/products/n otes_papers/mlfappnote.pdf . pinned vias for thermal conduction are not required for the low power psoc device. 001-13191 *e 001-50669 *b [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 34 of 43 thermal impedances capacitance on crystal pins solder reflow peak temperature this table lists the minimum solder reflow p eak temperature to achieve good solderability. table 34. thermal impedances per package package typical ja [42] 16 pin qfn 33 c/w 24 pin qfn [43] 21 c/w 32 pin qfn [43] 20 c/w 48 pin ssop 69 c/w 48 pin qfn [43] 18 c/w 30 ball wlcsp 54 c/w table 35. typical package capacitance on crystal pins package package capacitance 32 pin qfn 3.2 pf 48 pin qfn 3.3 pf table 36. solder reflow peak temperature package minimum peak temperature [44] maximum peak temperature 16 pin qfn 240 c 260 c 24 pin qfn 240 c 260 c 32 pin qfn 240 c 260 c 48 pin ssop 220 c 260 c 48 pin qfn 240 c 260 c 30 ball wlcsp 240 c 260 c note 42. t j = t a + power ja . 43. to achieve the thermal impedance specified for the qfn package, the center thermal pad must be soldered to the pcb ground pl ane. 44. higher temperatures may be required based on the solder me lting point. typical temperatures for solder are 220 5 o c with sn-pb or 245 5 o c with sn-ag-cu paste. refer to the solder manufacturer specifications [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 35 of 43 development tool selection software psoc designer? at the core of the psoc development software suite is psoc designer, used to generate psoc firmware applications. psoc designer is a microsoft? windows-based, integrated devel- opment environment for the programmable system-on-chip (psoc) devices. the psoc designer ide and application runs on windows xp and windows vista. this system provides design database management by project, an integrated debugger with in -circuit emulator, in-system programming support, and built-i n support for third-party assem- blers and c compilers. psoc designer also supports c language compilers developed specifically for the devices in the psoc family. psoc designer is available free of charge at http://www.cypress. com/psocdesigner and includes a free c compiler. psoc designer software subsystems you choose a base device to work with and then select different onboard analog and digital components called user modules that use the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. you configure the user modules for your chosen application and connect them to each other and to the proper pins. then you generate your project. this prepop- ulates your project with apis and libraries that you can use to program your application. the tool also supports easy development of multiple configura- tions and dynamic reconfigurat ion. dynamic reconfiguration allows for changing configurations at run time. code generation tools psoc designer supports multiple third-party c compilers and assemblers. the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. the choice is yours. assemblers. the assemblers allow assembly code to be merged seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers. c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all the features of c tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow the designer to read and program and read and write data memory, read and write i/o registers, read and write cpu registers, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory lo cations of interest. in-circuit emulator a low cost, high functionality in -circuit emulator (ice) is available for development support. this hardware has the capability to program single device s. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24mhz) operation. standard cypress psoc ide tools are available for debugging the cy8c20x36a/46a/66a/96a fam ily of parts. however, the additional trace length and a minimal ground plane in the flex- pod can create noise problems that make it difficult to debug the design. a custom bonded on-chip debug (ocd) device is available in a 48-pin qfn package. the ocd device is recom- mended for debugging designs that have high current and/or high analog accuracy requirements. the qfn package is compact and is connected to the ice through a high density connector. psoc programmer psoc programmer is flexible enough and is used on the bench in development and is also suitable for factory programming. psoc programmer works either as a standalone programming application or operates dire ctly from psoc designer. psoc programmer software is compatible with both psoc ice cube in-circuit emulator and psoc miniprog. psoc programmer is available free of cost at http://www.cypress.co m/psocprogrammer.. development kits all development kits are sold at the cypress online store. cy3215-dk basic development kit the cy3215-dk is for prototyp ing and development with psoc designer. this kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. psoc designer supports the adv ance emulation f eatures also. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66a family cat-5 adapter mini-eval programming board 110 ~ 240 v power supply, euro-plug adapter imagecraft c compiler (registration required) issp cable usb 2.0 cable and blue cat-5 cable 2 cy8c29466a-24pxi 28-pdip chip samples [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 36 of 43 evaluation tools all evaluation tools are sold at the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit enables the user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466a-24pxi pdip psoc device sample 28-pin cy8c27443a-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3210-psoceval1 the cy3210-psoceval1 kit feat ures an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466a-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable cy3280-20x66 universal capsense controller the cy3280-20x66 capsense controller kit is designed for easy prototyping and debug of cy8c20xx6a capsense family designs with pre-defined control circuitry and plug-in hardware. programming hardware and an i2c-to-usb bridge are included for tuning and data acquisition. the kit includes: cy3280-20x66 capsense controller board cy3240-i2usb bridge cy3210 miniprog1 programmer usb 2.0 retractable cable cy3280-20x66 kit cd device programmers all device programmers are purchased from the cypress online store. cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base three programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industria l case that is more robust than the miniprog in a production programming environment. note that cy3207issp needs special software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240 v power supply, euro-plug adapter usb 2.0 cable [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 37 of 43 accessories (emulation and programming) third party tools several tools have been specially designed by the following thir d-party vendors to accompany psoc devices during development an d production. specific details for each of these tools can be found at http://www.cypress.com under documentation > evaluation boards. build a psoc emulator into your board for details on how to emulate your circuit before going to volume production using an on-chip debug (ocd) non-production psoc device, refer application note debugging - build a psoc emulator into your board ? an2323 . table 37. emulation and programming accessories part number pin package flex-pod kit [45] foot kit [46] adapter [47] cy8c20236a-24lkxi 16 qfn cy3250-20246qfn cy3250-20246qfn-pod see note 43 cy8c20246a-24lkxi 16 qfn cy3250-20246qfn cy3250-20246qfn-pod see note 47 cy8c20336a-24lqxi 24 qfn cy3250-20346qfn cy3250-20346qfn-pod see note 43 cy8c20346a-24lqxi 24 qfn cy3250-20346qfn cy3250-20346qfn-pod see note 47 cy8c20396a-24lqxi 24 qfn not supported cy8c20436a-24lqxi 32 qfn cy3250-20466qfn cy3250-20466qfn-pod see note 43 cy8c20446a-24lqxi 32 qfn cy3250-20466qfn cy3250-20466qfn-pod see note 47 cy8c20466a-24lqxi 32 qfn cy3250-20466qfn cy3250-20466qfn-pod see note 47 cy8c20496a-24lqxi 32 qfn not supported cy8c20536a-24pvxi 48 ssop cy3250- 20566 cy3250-20566-pod see note 47 cy8c20546a-24pvxi 48 ssop cy3250- 20566 cy3250-20566-pod see note 47 CY8C20566A-24PVXI 48 ssop cy3250- 20566 cy3250-20566-pod see note 47 cy8c20636a-24ltxi 48 qfn cy3250-20666qfn cy3250-20666qfn-pod see note 47 cy8c20646a-24ltxi 48 qfn cy3250-20666qfn cy3250-20666qfn-pod see note 47 cy8c20666a-24ltxi 48 qfn cy3250-20666qfn cy3250-20666qfn-pod see note 47 note 45. flex-pod kit includes a practice flex-pod and a practice pcb, in addition to two flex-pods. 46. foot kit includes surface mount feet that can be soldered to the target pcb. 47. programming adapter converts non-dip pa ckage to dip footprint. specific details an d ordering information for each of the ada pters can be found at http://www.emulation.com . [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 38 of 43 ordering information the following table lists the cy8c20x36a/46a/66a/96a ps oc devices' key package features and ordering codes.. table 38. psoc device key features and ordering information package ordering code flash (bytes) sram (bytes) capsense blocks digital i/o pins analog inputs [ 48 ] xres pin usb adc 16-pin (3 3 0.6 mm) qfn cy8c20236a-24lkxi 8 k 1 k 1 13 13 yes no yes 16-pin (3 3 0.6 mm) qfn (tape and reel) cy8c20236a-24lkxit 8 k 1 k 1 13 13 yes no yes 16-pin (3 3 0.6 mm) qfn cy8c20246a-24lkxi 16 k 2 k 1 13 13 yes no yes 16-pin (3 3 0.6 mm) qfn (tape and reel) cy8c20246a-24lkxit 16 k 2 k 1 13 13 yes no yes 24-pin (4 4 0.6 mm) qfn cy8c20336a-24lqxi 8 k 1 k 1 20 20 yes no yes 24-pin (4 4 0.6 mm) qfn (tape and reel) cy8c20336a-24lqxit 8 k 1 k 1 20 20 yes no yes 24-pin (4 4 0.6 mm) qfn cy8c20346a-24lqxi 16 k 2 k 1 20 20 yes no yes 24-pin (4 4 0.6 mm) qfn (tape and reel) cy8c20346a-24lqxit 16 k 2 k 1 20 20 yes no yes 24-pin (4 4 0.6 mm) qfn cy8c20396a-24lqxi 16 k 2 k 1 19 19 yes yes yes 24-pin (4 4 0.6 mm) qfn (tape and reel) cy8c20396a-24lqxit 16 k 2 k 1 19 19 yes yes yes 32-pin (5 5 0.6 mm) qfn cy8c20436a-24lqxi 8 k 1 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn (tape and reel) cy8c20436a-24lqxit 8 k 1 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn cy8c20446a-24lqxi 16 k 2 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn (tape and reel) cy8c20446a-24lqxit 16 k 2 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn cy8c20466a-24lqxi 32 k 2 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn (tape and reel) cy8c20466a-24lqxit 32 k 2 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn cy8c20496a-24lqxi 16 k 2 k 1 25 25 yes yes yes 32-pin (5 5 0.6 mm) qfn (tape and reel) cy8c20496a-24lqxit 16 k 2 k 1 25 25 yes yes yes 48-pin ssop cy8c20536a-24pvxi 8 k 1 k 1 34 34 yes no yes 48-pin ssop (tape and reel) cy8c20536a-24pvxit 8 k 1 k 1 34 34 yes no yes 48-pin ssop cy8c20546a-24pvxi 16 k 2 k 1 34 34 yes no yes 48-pin ssop (tape and reel) cy8c20546a-24pvxit 16 k 2 k 1 34 34 yes no yes 48-pin ssop CY8C20566A-24PVXI 32 k 2 k 1 34 34 yes no yes 48-pin ssop (tape and reel) CY8C20566A-24PVXIt 32 k 2 k 1 34 34 yes no yes 48-pin (7 7 mm) qfn cy8c20636a-24ltxi 8 k 1 k 1 36 36 yes no yes 48-pin (7 7 mm) qfn (tape and reel) cy8c20636a-24ltxit 8 k 1 k 1 36 36 yes no yes 48-pin (7 7 mm) qfn cy8c20646a-24ltxi 16 k 2 k 1 36 36 yes yes yes 48-pin (7 7 mm) qfn (tape and reel) cy8c20646a-24ltxit 16 k 2 k 1 36 36 yes yes yes 48-pin (7 7 mm) qfn cy8c20666a-24ltxi 32 k 2 k 1 36 36 yes yes yes [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 39 of 43 ordering code definitions 48-pin (7 7 mm) qfn (tape and reel) cy8c20666a-24ltxit 32 k 2 k 1 36 36 yes yes yes 48-pin (7 7 mm) qfn (ocd) [48] cy8c20066a-24ltxi 32 k 2 k 1 36 36 yes yes yes 30-pin wlcsp cy8c20746a-24fdxc 16 k 1 k 1 27 27 yes no yes 30-pin wlcsp (tape and reel) cy8c20746a-24fdxct 16 k 1 k 1 27 27 yes no yes 30-pin wlcsp cy8c20766a-24fdxc 32 k 2 k 1 27 27 yes no yes 30-pin wlcsp (tape and reel) cy8c20766a-24fdxct 32 k 2 k 1 27 27 yes no yes 24-pin (4 4 0.6 mm) qfn cy8c20336an-24lqxi 8 k 1 k 1 20 20 yes no no 24-pin (4 4 0.6 mm) qfn (tape and reel) cy8c20336an- 24lqxit 8 k 1 k 1 20 20 yes no no 32-pin (5 5 0.6 mm) qfn cy8c20436an-24lqxi 8 k 1 k 1 28 28 yes no no 32-pin (5 5 0.6 mm) qfn (tape and reel) cy8c20436an- 24lqxit 8 k 1 k 1 28 28 yes no no 48-pin (7 7 mm) qfn cy8c20636an-24ltxi 8 k 1 k 1 36 36 yes no no 48-pin (7 7 mm) qfn (tape and reel) cy8c20636an-24ltxit 8 k 1 k 1 36 36 yes no no table 38. psoc device key features and ordering information package ordering code flash (bytes) sram (bytes) capsense blocks digital i/o pins analog inputs [ 48 ] xres pin usb adc note 48. dual-function digital i/o pins also connect to the common analog mux . [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 40 of 43 acronymns acronyms used the following table lists the acro nyms that are used in this document. reference documents technical reference manual for cy8c20xx6 devices in-system serial programmi ng (issp) protocol for 20xx6 ( an2026c ) host sourced serial programming for 20xx6 devices (an59389 ) document conventions units of measure ta b l e 4 0 lists all the abbreviations used to measure the psoc devices. table 39. acronyms used in this document acronym description ac alternating current adc analog-to-digital converter api application programming interface cmos complementary metal oxide semiconductor cpu central processing unit dac digital-to-analog converter dc direct current eop end of packet fsr full scale range gpio general purpose input/output gui graphical user interface i 2 c inter-integrated circuit ice in-circuit emulator idac digital analog converter current ilo internal low speed oscillator imo internal main oscillator i/o input/output issp in-system serial programming lcd liquid crystal display ldo low dropout (regulator) lsb least-significant bit lvd low voltage detect mcu micro-controller unit mips mega instructions per second miso master in slave out mosi master out slave in msb most-significant bit ocd on-chip debugger por power on reset ppor precision power on reset psrr power supply rejection ratio pwrsys power system psoc? programmable system-on-chip slimo slow internal main oscillator sram static random access memory snr signal to noise ratio qfn quad flat no-lead scl serial i2c clock sda serial i2c data sdata serial issp data spi serial peripheral interface ss slave select ssop shrink small outline package tc test controller usb universal serial bus usb d+ usb data + usb d- usb data- wlcsp wafer level chip scale package xtal crystal table 40. units of measure symbol unit of measure c degree celsius db decibels ff femto farad g gram hz hertz kb 1024 bytes kbit 1024 bits khz kilohertz ksps kilo samples per second k kilohm mhz megahertz m megaohm a microampere f microfarad h microhenry s microsecond w microwatts ma milli-ampere ms milli-second mv milli-volts na nanoampere ns nanosecond nv nanovolts w ohm pa picoampere pf picofarad pp peak-to-peak ppm parts per million ps picosecond sps samples per second s sigma: one standard deviation v volts w watt [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 41 of 43 numeric naming hexadecimal numbers are represented with all letters in uppercase wi th an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h?, ?b?, or 0x are decimal. glossary crosspoint connection connection between any gpio combination via analog multiplexer bus. differential non-linearity ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one lsb apart. differential non-linearity is a measure of the worst case deviation from the ideal 1 lsb step. hold time hold time is the time following a clock event during which the data input to a latch or flip- flop must remain stable in order to guarantee that the latched data is correct. i 2 c it is a serial multi-master bus used to connect low speed peripherals to mcu. integral nonlinearity it is a term describing the maximum deviation between the idea l output of a dac/adc and the actual output level. latch-up current current at which the latch-up test is conducted according to jesd78 standard ( at 125 degree celsius) power supply rejection ratio (psrr) the psrr is defined as th e ratio of the change in supply voltage to the corresponding change in output voltage of the device. scan the conversion of all sensor capacitances to digital values. setup time period r equired to prepare a device, machine, proc ess, or system for it to be ready to function. signal-to-noise ratio the ratio between a capacitive finger signal and system noise. spi serial peripheral interface is a synchronous serial data link standard. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. *e page 42 of 43 document history page document title: cy8c20x36a/46a/66a/96a capsense ? applications document number: 001-54459 revision ecn origin of change submi ssion date description of change ** 2737924 snv 07/14/09 new silicon and document *a 2764528 matt 09/16/2009 updated ac chip level specifications updated adc user module electr ical specifications table added note 5. added sr power_up parameter. updated ordering information. updated capacitance on crystal pins *b 2803229 vzd 11/10/09 added contents on page 3 . added note 6 on page 20. edited features section to include reference to incremental adc. *c 2846083 dst/kejo 01/12/2010 updated ac programming specifications on page 27 per cdt 56531 updated idd typical values in dc chip-level specifications on page 18 . added 30-pin wlcsp pin and package details added contents on page 2. *d 2935141 kejo/isw/sshh 03/05/2010 updated features on page 1 . added smartsense? on page 4 . updated psoc ? functional overview on page 4 . removed snr statement regarding on page 4 (analog multi- plexer section). updated on page 5 with the i2c enhanced slave interface point. removed references to ?system level? in designing with psoc designer on page 6 . changed tc clk and tc data to issp clk and issp data respectively in all the pinouts. modified notes in pinouts. updated 30-ball pin diagram. removed imo frequency trim options diagram in electrical specifications on page 17 . updated and formatted values in dc and ac specifications. updated ordering information table. updated 48-pin ssop package diagram. added 30-ball wlcsp package spec 001-50669. removed ac analog mux bus specifications section. added spi master and slave mode diagrams. modified definition for timing for fast/standard mode on the i2c bus on page 28 . updated thermal impedances on page 34 . combined development tools with development tool selection on page 35 . removed references to ?system level?. updated evaluation tools on page 36 . added ordering code definitions on page 39 . updated acronyms used on page 40 . added glossary and reference documents on page 40 changed datasheet status from preliminary to final *e 3043291 saac 09/30/10 1) change: added the line ?supports smartsense? under the ?low power capsense ? block? bullet in the features section. areas affected: features section. impact: helps to know that this part has the feature of auto tuning. 2) change: replaced pod mpns. areas affected: foot kit column of table 37. 3) change: template and styles update. areas affected: entire datasheet. impact: datasheet adheres to cypress standards. [+] feedback document number: 001-54459 rev. *e revised september 30, 2010 page 43 of 43 psoc designer? is a trademark and psoc? and capsense? are registered trademarks of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 ph ilips semiconductors has a new trade name - nxp semiconductors. all products and compan y names mentioned in this document may be the trademarks of their respective holders. cy8c20x36a/46a/66a/96a ? cypress semiconductor corporation, 2009-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback |
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